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for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 for small orders, phone 1-800-835-8769. general description the MAX1710/max1711 step-down controllers are intended for core cpu dc-dc converters in notebook computers. they feature a triple-threat combination of ultra-fast transient response, high dc accuracy, and high efficiency needed for leading-edge cpu core power supplies. maxim? proprietary quick-pwm quick-response, constant-on-time pwm control scheme handles wide input/output voltage ratios with ease and provides 100ns ?nstant-on?response to load transients while maintaining a relatively constant switching fre- quency. high dc precision is ensured by a 2-wire remote-sens- ing scheme that compensates for voltage drops in both ground bus and the supply rail. an on-board, digital-to- analog converter (dac) sets the output voltage in com- pliance with mobile pentium ii cpu specifications. the MAX1710 achieves high efficiency at a reduced cost by eliminating the current-sense resistor found in traditional current-mode pwms. efficiency is further enhanced by an ability to drive very large synchronous- rectifier mosfets. single-stage buck conversion allows these devices to directly step down high-voltage batteries for the highest possible efficiency. alternatively, 2-stage conversion (stepping down the +5v system supply instead of the battery) at a higher switching frequency allows the mini- mum possible physical size. the MAX1710 and max1711 are identical except that the max1711 has a 5-bit dac rather than a 4-bit dac. also, the max1711 has a fixed overvoltage protection threshold at v out = 2.25v and undervoltage protection at v out = 0.8v, whereas the MAX1710 has variable thresholds that track v out . the max1711 is intended for applications where the dac code may change dynamically. applications notebook computers docking stations cpu core dc-dc converters single-stage (batt to v core) converters two-stage (+5v to v core ) converters features ? ultra-high efficiency ? no current-sense resistor (lossless i limit ) ? quick-pwm with 100ns load-step response ? ?% v out accuracy over line and load ? 4-bit on-board dac (MAX1710) ? 5-bit on-board dac (max1711) ? 0.925v to 2v output adjust range (max1711) ? 2v to 28v battery input range ? 200/300/400/550khz switching frequency ? remote gnd and v out sensing ? over/undervoltage protection ? 1.7ms digital soft-start ? drives large synchronous-rectifier fets ? 2v ?% reference output ? power-good indicator ? small 24-pin qsop package MAX1710/max1711 high-speed, digitally adjusted step-down controllers for notebook cpus ________________________________________________________________ maxim integrated products 1 19-4781; rev 0; 11/98 pin configuration appears at end of data sheet. quick-pwm is a trademark of maxim integrated products. mobile pentium ii is a registered trademark of intel corp. -40? to +85? part MAX1710eeg temp. range pin-package 24 qsop ordering information max1711eeg -40? to +85? 24 qsop evaluation kit manual follows data sheet skip gnd dh lx dl bst +5v input ilim gnds fbs d0 d1 d2 d3 d4** *MAX1710 only **max1711 only ref cc pgnd fb MAX1710 max1711 v+ v cc ovp* v dd shdn output 0.925v to 2v (max1711) d/a inputs battery 4.5v to 28v minimal operating circuit
MAX1710/max1711 high-speed, digitally adjusted step-down contr ollers for notebook cpus 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v+ to gnd .............................................................. -0.3v to +30v v cc , v dd to gnd ..................................................... -0.3v to +6v pgnd to gnd ..................................................................... 0.3v shdn , pgood to gnd ........................................... -0.3v to +6v ovp, ilim, fb, fbs, cc, ref, d0?4, gnds, ton to gnd .............................. -0.3v to (v cc + 0.3v) skip to gnd (note 1) ................................. -0.3v to (v cc + 0.3v) dl to pgnd ................................................ -0.3v to (v dd + 0.3v) bst to gnd ............................................................ -0.3v to +36v dh to lx ..................................................... -0.3v to (bst + 0.3v) lx to bst .................................................................. -6v to +0.3v ref short circuit to gnd ........................................... continuous continuous power dissipation (t a = +70 c) 24-pin qsop (derate 9.5mw/ c above +70 c) .......... 762mw operating temperature range ........................... -40 c to +85 c junction temperature ...................................................... +150 c storage temperature range ............................. -65 c to +165 c lead temperature (soldering, 10sec) ............................. +300 c v batt = 4.5v to 28v, includes load regulation error shdn = 0, measured at v+ = 28v, v cc = v dd = 0 or 5v shdn = 0 v cc, v dd shdn = 0 battery voltage, v+ measured at v+ measured at v dd , fb forced above the regulation point measured at v cc , fb forced above the regulation point rising edge of shdn to full i lim (note 2) v batt = 24v, fb = 2v (note 2) fb (MAX1710 only) or fbs fb-fbs or gnds-gnd = 0 to 25mv v cc = 4.5v to 5.5v, v batt = 4.5v to 28v conditions a <1 5 shutdown battery supply current a <1 5 shutdown supply current (v dd ) a <1 5 shutdown supply current (v cc ) a 25 40 quiescent battery supply current a <1 5 quiescent supply current (v dd ) a 600 950 quiescent supply current (v cc ) ns 400 500 minimum off-time 380 425 470 260 290 320 175 200 225 % -1 1 dc output voltage accuracy ton = ref (400khz) 4.5 5.5 v 2 28 input voltage range ton = gnd (550khz) ns 140 160 180 on-time ms 1.7 soft-start ramp time a -1 1 gnds input bias current a -0.2 0.2 fb input bias current ton = open (300khz) mv 3 remote sense voltage error mv 5 line regulation error unit min typ max parameter falling edge, hysteresis = 40mv ref in regulation i ref = 0 to 50 a v cc = 4.5v to 5.5v, no external ref load v 1.6 ref fault lockout voltage a 10 ref sink current v 0.01 reference load regulation v 1.98 2 2.02 reference voltage ton = v cc (200khz) note 1: skip may be forced below -0.3v, temporarily exceeding the absolute maximum rating, for the purpose of debugging proto - type breadboards using the no-fault test mode. limit the current drawn to -5ma maximum. electrical characteristics (circuit of figure 1, v batt = 15v, v cc = v dd = 5v, skip = gnd, t a = 0 c to +85 c , unless otherwise noted.) k 130 180 240 fb input resistance (max1711) dac codes from 1.3v to 2v -1.2 1.2 i load = 0 to 7a mv 9 load regulation error dac codes from 0.925v to 1.275v
with respect to unloaded output voltage MAX1710/max1711 high-speed, digitally adjusted step-down contr ollers for notebook cpus _______________________________________________________________________________________ 3 electrical characteristics (continued) (circuit of figure 1, v batt = 15v, v cc = v dd = 5v, skip = gnd, t a = 0 c to +85 c , unless otherwise noted.) conditions unit min typ max parameter lx to pgnd lx to pgnd, ilim tied to v cc from shdn signal going high mv 40 50 60 current-limit threshold (positive direction, adjustable) mv 90 100 110 current-limit threshold (positive direction, fixed) ms 10 30 output undervoltage protection time % 65 70 75 output undervoltage protection threshold lx to pgnd, t a = +25 c mv -150 -120 -80 current-limit threshold (negative direction) r lim = 100k r lim = 400k 170 200 230 rising edge, hysteresis = 20mv, pwm disabled below this level v 4.1 4.4 v cc undervoltage lockout threshold bst-lx forced to 5v 5 dh gate-driver on-resistance dl, high state 5 dl gate-driver on-resistance (pull-up) dl, low state 0.5 1.7 dl gate-driver on-resistance (pull-down) dh forced to 2.5v, bst-lx forced to 5v a 1 dh gate-driver source/sink current dl forced to 2.5v a 3 dl gate-driver sink current dl forced to 2.5v a 1 dl gate-driver source current fb forced 2% above trip threshold s 1.5 overvoltage fault propagation delay % 10.5 12.5 14.5 overvoltage trip threshold fb forced 2% below pgood trip threshold, falling edge s 1.5 pgood propagation delay lx to pgnd mv 3 current-limit threshold (zero crossing) i sink = 1ma v 0.4 pgood output low voltage high state, forced to 5.5v a 1 pgood leakage current hysteresis = 10 c c 150 thermal shutdown threshold v 2.21 2.25 2.29 0.76 0.8 0.84 with respect to unloaded output voltage (MAX1710) with respect to unloaded output voltage (MAX1710) (max1711) v dl rising ns 35 dead time dh rising 26 ma skip input current logic threshold to enable no-fault mode, t a = +25 c -1.5 -0.1 % pgood trip threshold measured at fb with respect to unloaded output voltage, falling edge, hysteresis = 1% -8 -5 -3 v logic input high voltage d0?4, shdn , skip , ovp 2.4 v logic input low voltage d0?4, shdn , skip , ovp 0.8 a logic input current shdn , skip , ovp -1 1 a logic input pull-up current d0?4, each forced to gnd 3 5 10 (max1711)
MAX1710/max1711 high-speed, digitally adjusted step-down contr ollers for notebook cpus 4 _______________________________________________________________________________________ % 10 15 v batt = 4.5v to 28v, for all d/a codes, includes load regulation error v cc, v dd battery voltage, v+ measured at v cc , fb forced above the regulation point overvoltage trip threshold (note 2) v batt = 24v, fb = 2v (note 2) with respect to unloaded output voltage (MAX1710) % conditions 65 75 output undervoltage protection threshold a 950 quiescent supply current (v cc ) ns 500 minimum off-time 380 470 260 320 175 225 % -1.5 1.5 dc output voltage accuracy ton = ref (400khz) 4.5 5.5 v 2 28 input voltage range ton = gnd (550khz) ns 140 180 on-time ton = open (300khz) unit min typ max parameter v cc = 4.5v to 5.5v, no external ref load v 1.98 2.02 reference voltage ton = v cc (200khz) lx to pgnd, ilim tied to v cc mv 85 115 current-limit threshold (positive direction, fixed) lx to pgnd mv 35 65 current-limit threshold (positive direction, adjustable) r lim = 100k r lim = 400k 160 240 rising edge, hysteresis = 20mv, pwm disabled below this level 4.1 4.4 v cc undervoltage lockout threshold v d0?4, shdn , skip , ovp v 2.4 logic input high voltage d0?4, shdn , skip , ovp v 0.8 logic input low voltage shdn , skip , ovp a -1 1 logic input current d0?4, each forced to gnd a 3 10 logic input pull-up current electrical characteristics (circuit of figure 1, v batt =15v, v cc = v dd = 5v, skip = gnd, t a = -40 c to +85 c, unless otherwise noted.) (note 3) v 2.20 2.30 0.75 0.85 v electrical characteristics (continued) (circuit of figure 1, v batt = 15v, v cc = v dd = 5v, skip = gnd, t a = 0 c to +85 c , unless otherwise noted.) conditions ton logic input high level v v cc - 0.4 ton v cc level ton logic input upper-mid-range level v 3.15 3.85 ton float voltage ton logic input lower-mid-range level v 1.65 2.35 ton reference level ton logic input low level v 0.5 ton gnd level ton only, forced to gnd or v cc a -3 3 ton logic input current unit min typ max parameter with respect to unloaded output voltage (MAX1710) (max1711) (max1711) % -1.7 1.7 dac codes from 1.32v to 2v dac codes from 0.925v to 1.275v
MAX1710/max1711 high-speed, digitally adjusted step-down contr ollers for notebook cpus _______________________________________________________________________________________ 5 40 60 50 80 70 90 100 0.01 0.1 1 10 efficiency vs. load current (v o = 2.0v, f = 300khz) MAX1710-01 load current (a) efficiency (%) v in = 4.5v v in = 7v v in = 15v v in = 24v 40 60 50 80 70 90 100 0.01 0.1 1 10 efficiency vs. load current (v o = 1.6v, f = 300khz) MAX1710-02 load current (a) efficiency (%) v in = 4.5v v in = 24v v in = 7v v in = 15v 40 60 50 80 70 90 100 0.01 0.1 1 10 efficiency vs. load current (v o = 1.3v, f = 300khz) MAX1710-03 load current (a) efficiency (%) v in = 4.5v v in = 24v v in = 15v v in = 7v 40 60 50 80 70 90 100 0.01 0.1 1 10 efficiency vs. load current (v o = 1.6v, f = 550khz) MAX1710-04 load current (a) efficiency (%) v in = 4.5v v in = 15v v in = 7v v in = 24v 0 100 50 200 150 300 250 350 0.01 0.1 1 10 frequency vs. load current (v o = 1.6v) MAX1710-05 load current (a) frequency (khz) v in = 15v, pwm mode v in = 4.5v, skip mode v in = 15v, skip mode ton = open 300 306 304 302 308 310 312 314 316 318 320 0 10 5 15 20 25 30 frequency vs. input voltage (i o = 7a) MAX1710-06 input voltage (v) frequency (khz) v o = 2.0v v o = 1.6v ton = open note 2: on-time and off-time specifications are measured from 50% point to 50% point at the dh pin with lx forced to 0v, bst forced to 5v, and a 250pf capacitor connected from dh to lx. actual in-circuit times may differ due to mosfet switching speeds. note 3: specifications from -40 c to 0 c are guaranteed but not production tested. __________________________________________ t ypical operating characteristics (7a cpu supply circuit of figure 1, t a = +25 c, unless otherwise noted.) conditions measured at fb with respect to unloaded output voltage, falling edge, hysteresis = 1% % -8.5 -2.5 pgood trip threshold i sink = 1ma v 0.4 pgood output low voltage high state, forced to 5.5v a 1 pgood leakage current unit min typ max parameter electrical characteristics (continued) (circuit of figure 1, v batt =15v, v cc = v dd = 5v, skip = gnd, t a = -40 c to +85 c, unless otherwise noted.) (note 3)
MAX1710/max1711 high-speed, digitally adjusted step-down contr ollers for notebook cpus 6 _______________________________________________________________________________________ _____________________________ t ypical operating characteristics (continued) (7a cpu supply circuit of figure 1, t a = +25 c, unless otherwise noted.) 0 0.2 0.1 0.5 0.4 0.3 0.8 0.7 0.6 0.9 0 10 5 15 20 25 30 continuous to discontinuous inductor current point vs. input voltage MAX1710-10 input voltage (v) load current (a) v o = 2.0v v o = 1.6v v o = 1.3v 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 0 10 5 15 20 25 30 inductor current peaks and valleys vs. input voltage (at current-limit point) MAX1710-11 input voltage (v) inductor current (a) i peak i valley 0 0.2 0.1 0.4 0.3 0.6 0.5 0.7 0 5 15 25 10 20 30 no-load supply currents vs. input voltage (skip mode, f = 300khz) MAX1710-12 input voltage (v) supply current (ma) i cc i batt i dd 0 0.2 0.1 0.4 0.3 0.6 0.5 0.7 0 10 20 30 5 15 25 no-load supply currents vs. input voltage (skip mode, f = 550khz) MAX1710-13 input voltage (v) supply current (ma) i cc i batt i dd 0 6 4 2 8 10 12 14 16 18 20 0 10 5 15 20 25 30 no-load supply currents vs. input voltage (pwm mode, f = 300khz) MAX1710-14 input voltage (v) supply current (ma) i dd i bat i cc 0 6 4 2 8 10 12 14 16 18 20 0 10 5 15 20 25 30 no-load supply currents vs. input voltage (pwm mode, f = 550khz) MAX1710-15 input voltage (v) supply current (ma) i dd i bat i cc 285 290 295 300 305 310 315 -60 -20 -40 0 20 40 60 80 100 frequency vs. temperature (v in = 15v, v o = 2.0v) MAX1710-07 temperature (?) frequency (khz) i o = 7a i o = 4a i o = 1a ton = open 456 460 458 466 464 462 472 470 468 474 -60 0 20 -40 -20 40 60 80 100 on-time vs. temperature MAX1710-08 temperature (?) on time (ns) i o = 1a i o = 4a or 7a 0 5 10 15 20 25 30 -60 -20 -40 0 20 40 60 80 100 current-limit trip point vs. temperature MAX1710-09 temperature (?) current trip point (a) i lim = 400k w i lim = v cc i lim = 100k w
10 m s/div load-transient response (with integrator) v in = 15v, v o = 1.6v, i o = 0a to 7a a = v out , ac coupled, 50mv/div b = inductor current, 5a/div a b MAX1710-16 10 m s/div load-transient response (with integrator) v in = 15v, v o = 1.6v, i o = 30ma, to 7a a = v out , ac coupled, 50mv/div b = inductor current, 5a/div a b MAX1710-17 MAX1710/max1711 high-speed, digitally adjusted step-down contr ollers for notebook cpus _______________________________________________________________________________________ 7 _____________________________ t ypical operating characteristics (continued) (7a cpu supply circuit of figure 1, t a = +25 c, unless otherwise noted.) 20 m s/div load-transient response (with integrator) v in = 4.5v, v o = 2v, i o = 30ma to 7a a = v out , ac coupled, 50mv/div b = inductor current, 5a/div c = dl, 10v/div a b c MAX1710-19 20 m s/div load-transient response (with integrator) v in = 4.5v, v o = 1.3v, i o = 30ma to 7a a = v out , ac coupled, 50mv/div b = inductor current, 5a/div c = dl, 10v/div a b c MAX1710-20 500 m s/div start-up waveform a = shdn b = v out , 0.5v/div c = inductor current, 5a/div a b c MAX1710-21 10 m s/div load-transient response (without integrator) v in = 15v, v o = 1.6v, i o = 30ma to 7a a = v out , ac coupled, 50mv/div b = inductor current, 5a/div a b MAX1710-18
MAX1710/max1711 high-speed, digitally adjusted step-down contr ollers for notebook cpus 8 _______________________________________________________________________________________ 50 m s/div output overload waveform v out = 1.6v a = v in , ac coupled, 2v/div b = v out , 0.5v/div c = inductor current, 5a/div a b c MAX1710-22 5 m s/div load-transient response l = 0.7 m h, v out = 1.6v, v in = 15v, c out = 47 m f (x4), f = 550khz a = v out , ac coupled, 100mv/div b = inductor current, 5a/div c = dl, 5v/div a b c MAX1710-23 ceramic c out 5 m s/div shutdown waveform v in = 15v, v 0 = 1.6v, i 0 = 7a a = v out , 0.5v/div b = inductor current, 5a/div c = shdn, 2v/div d = dl, 5v/div a b c d MAX1710-24 _____________________________ t ypical operating characteristics (continued) (7a cpu supply circuit of figure 1, t a = +25 c, unless otherwise noted.) pin description name function 5 cc integrator capacitor connection. connect a 100pf to 1000pf (470pf typical) capacitor to gnd to set the integration time constant. pin 4 fbs feedback remote-sense input, normally connected to v out directly at the load. fbs internally connects to the integrator that fine-tunes the dc output voltage. tie fbs to v cc to disable all three integrator amplifiers. tie fbs to fb (or disable the integrators) when externally adjusting the output voltage with a resistor-divider. 3 fb fast feedback input, normally connected to v out . fb is connected to the bulk output filter capacitors local - ly at the power supply. an external resistor-divider can optionally set the output voltage. 8 ton on-time selection control input. this is a four-level input that sets the k factor to determine dh on-time. gnd = 550khz, ref = 400khz, open = 300khz, v cc = 200khz. 7 v cc analog supply voltage input for pwm core, 4.5v to 5.5v. bypass v cc to gnd with a 0.1 f minimum capacitor. 6 ilim current-limit threshold adjustment. connects to an external resistor to gnd. the lx-pgnd current-limit threshold defaults to +100mv if ilim is tied to v cc . the current-limit threshold is 1/10 of the voltage forced at ilim. in adjustable mode the threshold is v th = r lim 5 a/10. 1 cc battery voltage sense connection. v+ is used only for pwm one-shot timing. dh on-time is inversely propor - tional to v+ input voltage over a range of 2v to 28v. 9 ref 2.0v reference output. bypass ref to gnd with a 0.22 f minimum capacitor. ref can source 50 a for external loads. loading ref degrades fb accuracy according to the ref load-regulation error (see electrical characteristics ). 2 shdn shutdown control input, active low. shdn cannot withstand the battery voltage. in shutdown mode, dl is forced to v dd in order to enforce overvoltage protection, even when powered down (unless ovp is high).
MAX1710/max1711 high-speed, digitally adjusted step-down contr ollers for notebook cpus _______________________________________________________________________________________ 9 standar d application cir cuit the standard application circuit (figure 1) generates a low-voltage, high-power rail for supplying up to 7a to the core cpu v cc in a notebook computer. this dc-dc converter steps down a battery or ac adapter voltage to sub-2v levels with high efficiency and accuracy, and represents a good compromise between size, efficiency, and cost. see the MAX1710 ev kit manual for a list of components and suppliers. detailed description the MAX1710/max1711 buck controllers are targeted for low-voltage, high-current cpu power supplies for notebook computers. cpu cores typically exhibit 0 to 10a or greater load steps when the clock is throttled. the proprietary quick-pwm pulse-width modulator in the MAX1710/max1711 is specifically designed for han - dling these fast load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. the quick- pwm architecture circumvents the poor load-transient timing problems of fixed-frequency current-mode pwms pin description (continued) name function 16 (max1711 ) d4 dac code input, msb, 5 a internal pull-up to v cc (tables 1 and 2). pin 13 dl low-side gate-driver output, swings 0 to v dd . 12 pgood open-drain power-good output. 11 gnds ground remote-sense input, normally connected to ground directly at the load. gnds internally con - nects to the integrator that fine-tunes the ground offset voltage. 10 gnd analog ground 14 pgnd power ground. also used as the inverting input for the current-limit comparator. 15 v dd supply voltage input for the dl gate driver, 4.5v to 5.5v 17 d3 dac code input. 5 a internal pull-up to v cc . 16 (max171 0) ovp overvoltage-protection disable control input (table 3). gnd = normal operation and overvoltage protection active, v cc = overvoltage protection disabled. 22 bst boost flying-capacitor connection. an optional resistor in series with bst allows the dh pull-up current to be adjusted (figure 5). this technique of slowing the lx rise time can be used to prevent accidental turn-on of the low-side mosfet due to excessive gate-drain capacitance. 21 skip low-noise-mode selection control input. low-noise forced-pwm mode causes inductor current recirculation at light loads and suppresses pulse-skipping operation. normal operation prevents current recirculation. skip can also be used to disable both overvoltage and undervoltage protection circuits and clear the fault latch (figure 6). gnd = normal operation, v cc = low-noise mode. do not leave skip floating . 20 d0 dac code input lsb. 5 a internal pull-up. 19 d1 dac code input. 5 a internal pull-up. 18 d2 dac code input. 5 a internal pull-up. 24 dh high-side gate-driver output. swings lx to bst. 23 lx inductor connection. lx serves as the lower supply rail for the dh high-side gate driver. also used for the noninverting input to the current-limit comparator as well as the skip-mode zero-crossing com - parator.
MAX1710/max1711 while also avoiding the problems caused by widely vary - ing switching frequencies in conventional constant-on- time and constant-off-time pwm schemes. +5v bias supply (v cc and v dd ) the MAX1710/max1711 requires an external +5v bias supply in addition to the battery. typically, this +5v bias supply is the notebook? 95% efficient 5v system supply. keeping the bias supply external to the ic improves effi - ciency and eliminates the cost associated with the +5v linear regulator that would otherwise be needed to sup - ply the pwm circuit and gate drivers. if stand-alone capability is needed, the +5v supply can be generated with an external linear regulator such as the max1615. the battery and +5v bias inputs can be tied together if the input source is a fixed 4.5v to 5.5v supply. if the +5v bias supply is powered up prior to the battery supply, the enable signal ( shdn ) must be delayed until the battery voltage is present in order to ensure start-up. the +5v bias supply must provide v cc and gate-drive power, so the maximum current drawn is: i bias = i cc + f (q g1 + q g2 ) = 15ma to 30ma (typ) high-speed, digitally adjusted step-down contr ollers for notebook cpus 10 ______________________________________________________________________________________ v cc v batt 4.5v to 28v +5v bias supply c2 3 x 470 m f kemet t510 panasonic etqp6f2r0hfa power-good indicator * MAX1710 only ** max1711 only l1 2 m h v out 1.25v to 2v at 7a (MAX1710) 0.925v to 2v at 7a (max1711) shdn v+ 22 1 2 21 20 19 18 17 24 23 13 14 3 4 11 r4 1k 12 7 15 d2 cmpsh-3 c6 1 m f c7 0.1 m f c4 1 m f c3 470pf to v cc q1 d1 r2 100k d3 (optional ovp reverse-polarity clamp) q2 c5 1 m f r1 20 w c1 3 x 10 m f/30v skip d0 d1 d2 dac inputs on/off control low-noise control dl lx bst dh pgnd fb fbs gnds q1 = irf7807 q2 = irf7805 d1, d3 = mbrs130t3 (optional) c1 = sanyo os-con (30sc10m) pgood v dd MAX1710 max1711 8 9 5 6 16 +5v 10 d3 16 d4** ton ref cc gnd r3 (optional) ilim ovp* figure 1. standard application circuit
where i cc is 600 a typical, f is the switching frequency, and q g1 and q g2 are the mosfet data sheet total gate-charge specification limits at v gs = 5v. free-running, constant-on-time pwm controller with input feed-forward the quick-pwm control architecture is an almost fixed- frequency, constant-on-time current-mode type with volt - age feed-forward (figure 2). this architecture relies on the filter capacitor? esr to act as the current-sense resistor, so the output ripple voltage provides the pwm ramp signal. the control algorithm is simple: the high- side switch on-time is determined solely by a one-shot whose period is inversely proportional to input voltage and directly proportional to output voltage. another one- shot sets a minimum off-time (400ns typical). the on-time one-shot is triggered if the error comparator is low, the MAX1710/max1711 high-speed, digitally adjusted step-down contr ollers for notebook cpus ______________________________________________________________________________________ 11 ref -5% from d/a ref ref d0 d1 d2 d3 10k error amp toff ton ref +12% fb ref -30% r-2r d/a converter chip supply g m g m g m gnds cc shdn fbs pgood ovp/uvlo latch on-time compute ton 1-shot 1-shot trig v batt 2v to 28v trig q q s r 2v ref gnd ref fb pgnd +5v output dl v cc v cc v dd lx zero crossing current limit dh bst i lim r lim +5v 5 m a +5v q s1 q s2 timer skip ovp ton v+ 70k s MAX1710 s r q figure 2. MAX1710 functional diagram
MAX1710/max1711 high-speed, digitally adjusted step-down contr ollers for notebook cpus 12 ______________________________________________________________________________________ low-side switch current is below the current-limit thresh - old, and the minimum off-time one-shot has timed out. on-time one-shot (ton) the heart of the pwm core is the one-shot that sets the high-side switch on-time. this fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to battery and output voltage. the high-side switch on-time is inversely proportional to the battery voltage as measured by the v+ input, and directly pro - portional to the output voltage as set by the dac code. this algorithm results in a nearly constant switching fre - quency despite the lack of a fixed-frequency clock gen - erator. the benefits of a constant switching frequency are twofold: first, the frequency can be selected to avoid noise-sensitive regions such as the 455khz if band; second, the inductor ripple-current operating point remains relatively constant, resulting in easy design methodology and predictable output voltage ripple. on-time = k (v out + 0.075v) / v in where k is set by the ton pin-strap connection and 0.075v is an approximation to accommodate for the expected drop across the low-side mosfet switch. one-shot timing error increases for the shorter on-time settings due to fixed propagation delays and is approxi - mately 12.5% at 550khz and 400khz, and 10% at the two slower settings. this translates to reduced switch - ing-frequency accuracy at higher frequencies. (see table 5). switching frequency increases as a function of load current due to the increasing drop across the low- table 1. MAX1710 fb output voltage dac codes d3 d2 d1 d0 output voltage (v) 1 0 0 0 1.60 0 0 0 0 2.00 0 0 0 1 1.95 0 0 1 0 1.90 0 0 1 1 1.85 0 1 0 0 1.80 0 1 0 1 1.75 0 1 1 0 1.70 0 1 1 1 1.65 1 0 0 1 1.55 1 0 1 0 1.50 1 0 1 1 1.45 1 1 0 0 1.40 1 1 0 1 1.35 1 1 1 0 1.30 1 1 1 1 1.25 table 2. max1711 fb output voltage dac codes d4 d3 d2 d1 output voltage (v) 0 1 0 0 1.60 0 0 0 0 2.00 0 0 0 0 1.95 0 0 0 1 1.90 0 0 0 1 1.85 0 0 1 0 1.80 0 0 1 0 1.75 0 0 1 1 1.70 0 0 1 1 1.65 0 1 0 0 1.55 0 1 0 1 1.50 0 1 0 1 1.45 0 1 1 0 1.40 0 1 1 0 1.35 0 1 1 1 1.30 0 1 1 1 shutdown 3* 1 1 0 0 1.075 1 0 0 0 1.275 1 0 0 0 1.250 1 0 0 1 1.225 1 0 0 1 1.200 1 0 1 0 1.175 1 0 1 0 1.150 1 0 1 1 1.125 1 0 1 1 1.100 1 1 0 0 1.050 1 1 0 1 1.025 1 1 0 1 1.000 1 1 1 0 0.975 1 1 1 0 0.950 1 1 1 1 0.925 1 1 1 1 shutdown 3* d0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 * see table 3
MAX1710/max1711 high-speed, digitally adjusted step-down contr ollers for notebook cpus ______________________________________________________________________________________ 13 side mosfet, which causes a faster inductor-current discharge ramp. the on-times guaranteed in the electrical characteristics are influenced by switching delays in the external high-side power mosfet. the exact switching frequency will depend on gate charge, internal gate resistance, source inductance, and dh out - put drive characteristics. two external factors that can influence switching-fre - quency accuracy are resistive drops in the two conduc - tion loops (including inductor and pc board resistance) and the dead-time effect. these effects are the largest contributors to the change of frequency with changing load current. the dead-time effect is a notable disconti - nuity in the switching frequency as the load current is varied (see typical operating characteristics ). it occurs whenever the inductor current reverses, most commonly at light loads with skip high. with reversed inductor cur - rent, the inductor? emf causes lx to go high earlier than normal, extending the on-time by a period equal to the low-to-high dead time. for loads above the critical conduction point, the actual switching frequency is: where v drop1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and pc board resistances; v drop2 is the sum of the resistances in the charging path, and t on is the on-time calculated by the MAX1710/max1711. integrator amplifiers (cc) there are three integrator amplifiers that provide a fine adjustment to the output regulation point. one amplifier monitors the difference between gnds and gnd, while another monitors the difference between fbs and fb. the third amplifier integrates the difference between ref and the dac output. these three transconductance amplifiers?outputs are directly summed inside the chip, so the integration time constant can be set easily with a capacitor. the g m of each amplifier is 160 mho (typical). the integrator block has an ability to move and correct the output voltage by about -2%, +4%. for each amplifi - er, the differential input voltage range is about 50mv total, including dc offset and ac ripple. the voltage gain of each integrator is about 80v/v. the fbs amplifier corrects for dc voltage drops in pc board traces and connectors in the output bus path between the dc-dc converter and the load. the gnds amplifier performs a similar dc correction task for the output ground bus. the third amplifier provides an aver - aging function that forces v out to be regulated at the average value of the output ripple waveform. if the inte - grator amplifiers are disabled, v out is regulated at the valleys of the output ripple waveform. this creates a slight load-regulation characteristic in which the output voltage rises approximately 1% (up to 1/2 the peak amplitude of the ripple waveform as a limit) when under light loads. integrators have both beneficial and detrimental charac - teristics. while they do correct for drops due to dc bus resistance and tighten the dc output voltage tolerance limits by averaging the peak-to-peak output ripple, they can interfere with achieving the fastest possi - ble load-transient response. the fastest transient response is achieved when all three integrators are dis - abled. this works very well when the MAX1710/ max1711 circuit can be placed very close to the cpu. there is often a connector, or at least many milliohms of pc board trace resistance, between the dc-dc convert - er and the cpu. in these cases, the best strategy is to place most of the bulk bypass capacitors close to the cpu, with just one capacitor on the other side of the connector near the MAX1710/max1711 to control ripple if the cpu card is unplugged. in this situation, the remote-sense lines and integrators provide a real benefit. when both gnds and fbs are tied to v cc so that all three integrators are disabled, cc can be left uncon - nected, which eliminates a component. automatic pulse-skipping switchover at light loads, an inherent automatic switchover to pfm takes place. this switchover is effected by a comparator that truncates the low-side switch on-time at the inductor current? zero crossing. this mechanism causes the threshold between pulse-skipping pfm and non-skip - ping pwm operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the ?ritical conduction?point; see continuous to discontinuous inductor current point vs. input voltage graphs in the typical operating characteristics ). for a battery range of 7v to 24v this threshold is relatively constant, with only a minor depen - dence on battery voltage. where k is the on-time scale factor (see table 5). the load-current level at which pfm/pwm crossover occurs, i load(skip) , is equal to 1/2 the peak-to-peak ripple cur - rent, which is a function of the inductor value (figure 3). for example, in the standard application circuit with t on = 300ns at 24v, v out = 2v, and l = 2 h, switchover to pulse-skipping operation occurs at i load = 1.65a or i k l load skip ( ) ? 2 f v v t v v out drop on in drop = + + ( ) 1 2
MAX1710/max1711 high-speed, digitally adjusted step-down contr ollers for notebook cpus 14 ______________________________________________________________________________________ figure 4. valley current-limit threshold point inductor current i limit i load 0 time lx-pgnd i limit threshold = 100mv (nominal, default) voltage drop across q2 -i peak about 1/4 full load. the crossover point occurs at an even lower value if a swinging (soft-saturation) inductor is used. the switching waveforms may appear noisy and asyn - chronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. trade-offs in pfm noise vs. light-load efficiency can be made by varying the inductor value. generally, low inductor values pro - duce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. penalties for using higher inductor values include larger physical size and degraded load-transient response (especially at low input voltage levels). forced-pwm mode ( s s k k i i p p = high) the low-noise, forced-pwm mode ( skip driven high) dis - ables the zero-crossing comparator, which controls the low-side switch on-time. this causes the low-side gate- drive waveform to become the complement of the high- side gate-drive waveform. this in turn causes the inductor current to reverse at light loads, as the pwm loop strives to maintain a duty ratio of v out /v in . the benefit of forced-pwm mode is to keep the switching fre - quency fairly constant, but it comes at a cost: the no- load battery current can be as high as 40ma or more. forced-pwm mode is most useful for reducing audio-fre - quency noise, improving load-transient response, pro - viding sink-current capability for dynamic output voltage adjustment, and improving the cross-regulation of multi - ple-output applications that use a flyback transformer or coupled inductor. current-limit circuit (ilim) the current-limit circuit employs a unique ?alley?cur - rent-sensing algorithm that uses the on-state resistance of the low-side mosfet as a current-sensing element. if the current-sense signal is above the current-limit threshold, the pwm is not allowed to initiate a new cycle (figure 4). the actual peak current is greater than the current-limit threshold by an amount equal to the induc - tor ripple current. therefore the exact current-limit char - acteristic and maximum load capability are a function of the mosfet on-resistance, inductor value, and battery voltage. the reward for this uncertainty is robust, loss - less overcurrent sensing. when combined with the uvp protection circuit, this current-limit method is effective in almost every circumstance. there is also a negative current limit that prevents exces - sive reverse inductor currents when v out is sinking cur - rent. the negative current-limit threshold is set to approximately 120% of the positive current limit, and therefore tracks the positive current limit when ilim is adjusted. the current-limit threshold can be adjusted with an exter - nal resistor (r lim ) at ilim. a precision 5 a pull-up cur - rent source at ilim sets a voltage drop on this resistor, adjusting the current-limit threshold from 50mv to 200mv. in the adjustable mode, the current-limit thresh - old voltage is precisely 1/10th the voltage seen at ilim. therefore, choose r lim equal to 2k /mv of the current- limit threshold. the threshold defaults to 100mv when ilim is tied to v cc . the logic threshold for switchover to the 100mv default value is approximately v cc - 1v. the adjustable current limit can accommodate mosfets with atypical on-resistance characteristics (see design procedure ). a capacitor in parallel with r lim can provide a variable soft-start function. carefully observe the pc board layout guidelines to ensure that noise and dc errors don? corrupt the cur - rent-sense signals seen by lx and pgnd. the ic must be mounted close to the low-side mosfet with short, figure 3. pulse-skipping/discontinuous crossover point inductor current i load = i peak /2 on-time 0 time -i peak l v batt -v out d i d t =
MAX1710/max1711 high-speed, digitally adjusted step-down contr ollers for notebook cpus ______________________________________________________________________________________ 15 direct traces making a kelvin sense connection to the source and drain terminals. mosfet gate drivers (dh, dl) the dh and dl drivers are optimized for driving moder - ate-size, high-side and larger, low-side power mosfets. this is consistent with the low duty factor seen in the notebook cpu environment, where a large v batt - v out differential exists. an adaptive dead-time circuit monitors the dl output and prevents the high-side fet from turn - ing on until dl is fully off. there must be a low-resis - tance, low-inductance path from the dl driver to the mosfet gate in order for the adaptive dead-time circuit to work properly. otherwise, the sense circuitry in the MAX1710/max1711 will interpret the mosfet gate as ?ff?while there is actually still charge left on the gate. use very short, wide traces measuring 10 to 20 squares (50 to 100 mils wide if the mosfet is 1 inch from the MAX1710/max1711). the dead time at the other edge (dh turning off) is deter - mined by a fixed 35ns (typical) internal delay. the internal pull-down transistor that drives dl low is robust, with a 0.5 typical on-resistance. this helps pre - vent dl from being pulled up during the fast rise-time of the inductor node, due to capacitive coupling from the drain to the gate of the massive low-side synchronous- rectifier mosfet. however, you might still encounter some combinations of high- and low-side fets that will cause excessive gate-drain coupling, which can lead to efficiency-killing, emi-producing shoot-through currents. this can often be remedied by adding a resistor in series with bst, which increases the turn-on time of the high- side fet without degrading the turn-off time. dac converter (d0?4) the digital-to-analog converter (dac) programs the out - put voltage. it receives a digital code from pins on the cpu module that are either hard-wired to gnd or left open-circuit. note that the codes don? match any desk - top vrm codes. the MAX1710/max1711 contain weak internal pull-ups on each input in order to eliminate exter - nal resistors. when changing MAX1710 dac codes while powered up, the over/undervoltage protection features can be activated if the code is changed more than 1lsb at a time. for applications needing the capability of changing dac codes ?n-the-fly,?use the max1711. por, uvlo, and soft-start power-on reset (por) occurs when v cc rises above approximately 2v, resetting the fault latch and soft-start counter, and preparing the pwm for operation. v cc undervoltage lockout (uvlo) circuitry inhibits switching and forces the dl gate driver high (in order to enforce output overvoltage protection) until v cc rises above 4.2v, whereupon an internal digital soft-start timer begins to ramp up the maximum allowed current limit. the ramp occurs in five steps: 20%, 40%, 60%, 80%, and 100%, with 100% current available after 1.7ms 50%. a continuously adjustable, analog soft-start function can be realized by adding a capacitor in parallel with r lim at ilim. this soft-start method requires a minimum interval between power-down and power-up to allow r lim to dis - charge the capacitor. power-good output (pgood) the output (fb) is continuously monitored for undervolt - age by the pgood comparator, except in shutdown or standby mode. the -5% undervoltage trip threshold is measured with respect to the nominal unloaded output voltage, as set by the dac. if the dac code increases in steps greater than 1lsb, it is likely that pgood will momentarily go low. in shutdown and standby modes, pgood is actively held low. the pgood output is a true open-drain type with no parasitic esd diodes. note that the pgood undervoltage detector is completely inde - pendent of the output uvp fault detector. output overvoltage protection (ovp) the overvoltage protection circuit is designed to protect against a shorted high-side mosfet by drawing high current and blowing the battery fuse. the fb node is continuously monitored for overvoltage. the overvoltage trip threshold tracks the dac code setting. if the output is more than 12.5% above the nominal regulation point for the MAX1710 (2.25v absolute for the max1711), overvoltage protection (ovp) is triggered and the circuit shuts down. the dl low-side gate-driver output is then latched high until shdn is toggled or v cc power is cycled below 1v. this action turns on the synchronous- rectifier mosfet with 100% duty and, in turn, rapidly dis - charges the output filter capacitor and forces the output to ground. if the condition that caused the overvoltage (such as a shorted high-side mosfet) persists, the battery fuse will blow. note that dl going high can have the effect of causing output polarity reversal, due to energy stored in the output lc at the instant ovp activates. if the load can? tolerate being forced to a negative voltage, it may be desirable to place a power schottky diode across the output to act as a reverse-polarity clamp (figure 1). the MAX1710/max1711 itself can be affected by the fb pin going below ground, with the negative voltage coupling into shdn . it may be necessary to add 1k resistors in series with fb and fbs (figure 7).
MAX1710/max1711 high-speed, digitally adjusted step-down contr ollers for notebook cpus 16 ______________________________________________________________________________________ dl is also kept high continuously when v cc uvlo is active as well as in shutdown1 mode (table 3). overvoltage protection can be defeated via the ovp input (MAX1710 only) or via a skip test mod e (se e pin description ). output undervoltage protection (uvp) the output undervoltage protection function is similar to foldback current limiting, but employs a timer rather than a variable current limit. if the MAX1710 output (fb) is under 70% of the nominal value 20ms after coming out of shutdown, the pwm is latched off and won? restart until v cc power is cycled or shdn is toggled. for the max1711, the nominal uvp trip threshold is fixed at 0.8v. no-fault test mode the over/undervoltage protection features can compli - cate the process of debugging prototype breadboards, since there are (at most) a few milliseconds in which to determine what went wrong. therefore, a test mode is provided to totally disable the ovp, uvp, and thermal shutdown features, and clear to the fault latch if it has been previously set. the pwm operates as if skip were grounded (pfm/pwm mode). the no-fault test mode is entered by sinking 1.5ma from skip via an external negative voltage source in series with a resistor (figure 6). skip is clamped to gnd with a silicon diode, so choose the resistor value equal to (v force - 0.65v) / 1.5ma. design pr ocedur e firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple current ratio). the prima - shdn skip ovp dl mode comments 1 x 0 x 0 high shutdown1 low-power shutdown state. dl is forced to v dd , enforcing ovp. i cc < 1 a typ. x low 0 x 1 low shutdown2 low-power shutdown state. dl is forced to gnd, disabling ovp. i cc < 1 a typ. exiting shutdown triggers a soft-start cycle. shutdown3 (max1711 only) dac code = x1111 (see table 2) dl is forced to pgnd, dh is forced to lx. the max1711 eventually goes into uvp fault mode as the load current discharges the output. 1 below gnd x switching no fault test mode with ovp, uvp, and thermal faults disabled and latches cleared. otherwise normal operation, with automatic pwm/pfm switchover for pulse skipping at light loads (figure 6). 1 x 1 switching no ovp ovp faults disabled and ovp latch cleared. otherwise normal operation, with skip controlling pwm/pfm switchover. 1 v cc x switching run (pwm), low noise low-noise operation with no automatic switchover. fixed-frequency pwm action is forced regardless of load. inductor current reverses at light load levels. i cc draw = 750 a typ. i dd draw = 15ma typ. 1 gnd x switching run (pfm/pwm) normal operation with automatic pwm/pfm switchover for pulse skipping at light loads. i cc = 600 a typ. i dd draw = load dependent. 1 x x high fault fault latch has been set by ovp, output uvlo, or thermal shutdown. device will remain in fault mode until v cc power is cycled, skip is forced below ground, or shdn is toggled. table 3. operating mode truth table good operating point for compound buck designs or desktop circuits. +5v-input notebook cpu core 550 400 3-cell li+ notebook cpu core useful in 4-cell systems for lighter loads than the cpu or where size is key. considered mainstream by current standards. 4-cell li+ notebook cpu core 300 200 4-cell li+ notebook cpu core use for absolute best efficiency. comment typical application frequency (khz) table 4. frequency selection guidelines
MAX1710/max1711 ______________________________________________________________________________________ 17 high-speed, digitally adjusted step-down contr ollers for notebook cpus ry design trade-off lies in choosing a good switching fre - quency and inductor operating point, and the following four factors dictate the rest of the design: 1) input voltage range . the maximum value (v batt(max) ) must accommodate the worst-case high ac adapter voltage. the minimum value (v batt(min) ) must account for the lowest battery voltage after drops due to connectors, fuses, and battery selector switches. if there is a choice at all, lower input volt - ages result in better efficiency. 2) maximum load current . there are two values to con - sider. the peak load current (i load(max) ) determines the instantaneous component stresses and filtering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. the continuous load cur - rent (i load ) determines the thermal stresses and thus drives the selection of input capacitors, mosfets, and other critical heat-contributing com - ponents. modern notebook cpus generally exhibit i load = i load(max) 80%. 3) switching frequency . this choice determines the basic trade-off between size and efficiency. the opti - mal frequency is largely a function of maximum input voltage, due to mosfet switching losses that are proportional to frequency and vbatt 2 . the optimum frequency is also a moving target, due to rapid improvements in mosfet technology that are making higher frequencies more practical (table 4). 4) inductor operating point . this choice provides trade-offs between size vs. efficiency. low inductor values cause large ripple currents, resulting in the smallest size, but poor efficiency and high output noise. the minimum practical inductor value is one that causes the circuit to operate at the edge of criti - cal conduction (where the inductor current just touch - es zero with every cycle at maximum load). inductor values lower than this grant no further size-reduction benefit. the MAX1710/max1711? pulse-skipping algorithm initiates skip mode at the critical-conduction point. so, the inductor operating point also determines the load- current value at which pfm/pwm switchover occurs. the optimum point is usually found between 20% and 50% ripple current. the inductor ripple current also impacts transient- response performance, especially at low v batt - v out differentials. low inductor values allow the inductor cur - rent to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. the amount of output sag is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time: inductor selection the switching frequency (on-time) and operating point (% ripple or lir) determine the inductor value as follows: example: i load(max) = 7a, v out = 2v, f = 300khz, 50% ripple current or lir = 0.5. find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice, although powdered iron l v khz a = = m m 2 300 0 5 7 1 9 2 . . ( ) h h l v f lir i out load max = ( ) v i l c duty v v sag load max f batt min out = - ( ) ( ) ( ) ( ) d 2 2 bst +5v v batt 5 w dh lx MAX1710 max1711 figure 5. reducing the switching-node rise time approximately -0.65v 1.5ma v force skip gnd MAX1710 max1711 figure 6. disabling over/undervoltage protection (test mode)
MAX1710/max1711 high-speed, digitally adjusted step-down contr ollers for notebook cpus 18 ______________________________________________________________________________________ is cheap and can work well at 200khz. the core must be large enough not to saturate at the peak inductor current (i peak ). i peak = i load(max) + (lir / 2) i load(max) setting the current limit the minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. the valley of the inductor current occurs at i load(max) minus half of the ripple current, therefore: i limit(low) > i load(max) - (lir / 2) i load(max) where i limit(low) = minimum current-limit threshold volt - age divided by the r ds(on) of q2. for the MAX1710, the minimum current-limit threshold (100mv default setting) is 90mv. use the worst-case maximum value for r ds(on) from the mosfet q2 data sheet, and add some margin for the rise in r ds(on) with temperature. a good general rule is to allow 0.5% additional resistance for each c of temperature rise. examining the 7a notebook cpu circuit example with a maximum r ds(on) = 15m at high temperature reveals the following: i limit(low) = 90mv / 15m = 6a 6a is greater than the valley current of 5.25a, so the cir - cuit can easily deliver the full rated 7a using the default 100mv nominal ilim threshold. when adjusting the current limit, use a 1% tolerance r lim resistor to prevent a significant increase of errors in the current-limit tolerance. output capacitor selection the output filter capacitor must have low enough effective series resistance (esr) to meet output ripple and load- transient requirements, yet have high enough esr to sat - isfy stability requirements. also, the capacitance value must be high enough to absorb the inductor energy going from a full-load to no-load condition without tripping the overvoltage protection circuit. in cpu v core converters and other applications where the output is subject to violent load transients, the output capacitor? size depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance: in non-cpu applications, the output capacitor? size depends on how much esr is needed to maintain an acceptable level of output voltage ripple: the actual microfarad capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usually selected by esr and voltage rating rather than by capacitance value (this is true of tantalums, os-cons, and other electrolytics). when using low-capacity filter capacitors such as ceram - ic or polymer types, capacitor size is usually determined by the capacity needed to prevent the overvoltage pro - tection circuit from being tripped when transitioning from a full-load to a no-load condition. the capacitor must be large enough to prevent the inductor? stored energy from launching the output above the overvoltage protection threshold. generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the ris - ing load edge is no longer a problem (see also v sag equation under design procedure ). with integrators disabled, the amount of overshoot due to stored inductor energy can be calculated as: where i peak is the peak inductor current. to absolutely minimize the overshoot, disable the integrator first, since the inherent delay of the integrator can cause extra ?un- on?switching cycles to occur after the load change. output capacitor stability considerations stability is determined by the value of the esr zero rela - tive to the switching frequency. the point of instability is given by the following equation: for a typical 300khz application, the esr zero frequency must be well below 95khz, preferably below 50khz. tantalum and os-con capacitors in widespread use at the time of publication have typical esr zero frequencies of 15khz. in the design example used for inductor selec - tion, the esr needed to support 50mvp-p ripple is 50mv/3.5a = 14.2m . three 470 f/4v kemet t510 low- esr tantalum capacitors in parallel provide 15m max esr. their typical combined esr results in a zero at 14.1khz, well within the bounds of stability. f f where f r c esr esr esr f = = p p 1 2 d v c v l i c v out out 2 peak 2 out out = + ? ? ? ? ? - r vp p lir i esr load max - ( ) r v i esr dip load max ( )
MAX1710/max1711 high-speed, digitally adjusted step-down contr ollers for notebook cpus ______________________________________________________________________________________ 19 don? put high-value ceramic capacitors directly across the fast feedback inputs (fb to gnd) without taking pre - cautions to ensure stability. large ceramic capacitors can have a high esr zero frequency and cause erratic, unstable operation. however, it? easy to add enough series resistance simply by placing the capacitors a cou - ple of inches downstream from the junction of the induc - tor and fb pin (see the all-ceramic-capacitor application section). unstable operation manifests itself in two related but dis - tinctly different ways: double-pulsing and fast-feedback loop instability. double-pulsing occurs due to noise on fb or because the esr is so low that there isn? enough voltage ramp in the output voltage (fb) signal. this ?ools?the error com - parator into triggering a new cycle immediately after the 400ns minimum off-time period has expired. double- pulsing is more annoying than harmful, resulting in noth - ing worse than increased output ripple. however, it can indicate the possible presence of loop instability, which is caused by insufficient esr. loop instability can result in oscillations at the output after line or load perturbations that can trip the overvolt - age protection latch or cause the output voltage to fall below the tolerance limit. t he easiest method for checking stability is to apply a very fast zero-to-max load transient (see MAX1710 evaluation kit manual) and carefully observe the output voltage ripple envelope for overshoot and ringing. it can help to simultaneously monitor the inductor current with an ac current probe. don? allow more than one cycle of ringing after the initial step-response under- or overshoot . input capacitor selection the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents. non-tantalum chemistries (ceramic, aluminum, or os- con) are preferred due to their resistance to power-up surge currents. power mosfet selection most of the following mosfet guidelines focus on the challenge of obtaining high load-current capability (>5a) when using high-voltage (>20v) ac adapters. low-cur - rent applications usually require less attention. for maximum efficiency, choose a high-side mosfet (q1) that has conduction losses equal to the switching losses at the optimum battery voltage (15v). check to ensure that the conduction losses at minimum input volt - age don? exceed the package thermal limits or violate the overall thermal budget. check to ensure that con - duction losses plus switching losses at the maximum input voltage don? exceed the package ratings or violate the overall thermal budget. choose a low-side mosfet (q2) that has the lowest possible r ds(on) , comes in a moderate to small pack - age (i.e., so-8), and is reasonably priced. ensure that the MAX1710/max1711 dl gate driver can drive q2; in other words, check that the gate isn? pulled up by the high-side switch turning on due to parasitic drain-to-gate capacitance, causing cross-conduction problems. switching losses aren? an issue for the low-side mos - fet, since it? a zero-voltage switched device when used in the buck topology. mosfet power dissipation worst-case conduction losses occur at the duty factor extremes. for the high-side mosfet, the worst-case power dissipation due to resistance occurs at minimum battery voltage: pd(q1) = (v out / v batt(min) ) i load 2 r ds(on) generally, a small high-side mosfet is desired in order to reduce switching losses at high input voltages. however, the r ds(on) required to stay within package power-dissipation limits often limits how small the mos - fet can be. again, the optimum occurs when the switch - ing (ac) losses equal the conduction (r ds(on) ) losses. high-side switching losses don? usually become an issue until the input is greater than approximately 15v. switching losses in the high-side mosfet can become an insidious heat problem when maximum ac adapter voltages are applied, due to the squared term in the cv 2 f switching loss equation. if the high-side mosfet you?e chosen for adequate r ds(on) at low battery volt - ages becomes extraordinarily hot when subjected to v batt(max) , you must reconsider your choice of mos - fet. calculating the power dissipation in q1 due to switching losses is difficult, since it must allow for difficult to quanti - fy factors that influence the turn-on and turn-off times. these factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and pc board layout characteristics. the following switching loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including a sanity check using a thermocouple mounted on q1. i i v (v v ) v rms load out batt out batt = - ? ? ? ?
MAX1710/max1711 high-speed, digitally adjusted step-down contr ollers for notebook cpus 20 ______________________________________________________________________________________ where c rss is the reverse transfer capacitance of q1 and i gate is the peak gate-drive source/sink current (1a typical). for the low-side mosfet, q2, the worst-case power dis - sipation always occurs at maximum battery voltage: pd(q2) = (1 - v out / v batt(max) ) i load 2 r ds(on) the absolute worst case for mosfet power dissipation occurs under heavy overloads that are greater than i load(max) but are not quite high enough to exceed the current limit and cause the fault latch to trip. to protect against this possibility, you must ?verdesign?the circuit to tolerate i load = i limit(high) + (lir / 2) i load(max) , where i limit(high) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. this means that the mosfets must be very well heatsinked. if short-circuit protection without overload protection is enough, a nor - mal i load value can be used for calculating component stresses. choose a schottky diode d1 having a forward voltage low enough to prevent the q2 mosfet body diode from turning on during the dead time. as a general rule, a diode having a dc current rating equal to 1/3 of the load current is sufficient. this diode is optional, and if efficien - cy isn? critical it can be removed. application issues dropout performance the output voltage adjust range for continuous-conduc - tion operation is restricted by the non-adjustable 500ns (max) minimum off-time one-shot. for best dropout per - formance, use the slowest (200khz) on-time setting. when working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off-times. manufacturing tolerances and internal ( ) ( ) pd switching c v f i i rss batt max load gate = 2 v+ v cc v in = 7v to 24v* shdn skip ref dac inputs on/off cc 0.22 m f 470pf dl d0 lx bst 5 w dh pgnd gnd fb q1 +5v 20 w 0.1 m f 1 m f q2 0.5 m h 0.1 m f 1nf c1 1k r1 c2 cpu 1.6v at 7a 1k 1k v dd fbs gnds max1711 r2 c1 = 4 x 4.7 m f/25v taiyo yuden (tmk325bj475k) c2 = 6 x 47 m f/10v taiyo yuden (lmk550bj476km) r1 + r2 = 5m w minimum of pcb trace resistance (total) d1 d2 d3 d4 ton * for higher minimum input voltage, * less output capacitance is required. figure 7. all-ceramic-capacitor application ton setting (khz) approximate k-factor error (%) min v batt at v out = 2v (v) 200 10 2.6 300 10 2.9 400 12.5 3.2 550 12.5 3.6 k factor ( s-v) 5 3.3 2.5 1.8 table 5. approximate k-factors errors
propagation delays introduce an error to the ton k-fac - tor. this error is higher at higher frequencies (table 5). also, keep in mind that transient response performance of buck regulators operated close to dropout is poor, and bulk output capacitance must often be added (see v sag equation in the design procedure ). dropout design example: v batt = 3v min, v out = 2v, f = 300khz. the required duty is (v out + v sw ) / (v batt - v sw ) = (2v + 0.1v) / (3.0v - 0.1v) = 72.4%. the worst-case on-time is (v out + 0.075) / v batt k = 2.075v / 3v 3.35 s-v 90% = 2.08 s. the ic duty-fac - tor limitation is: which meets the required duty. remember to include inductor resistance and mosfet on-state voltage drops (v sw ) when doing worst-case dropout duty-factor calculations. all-ceramic-capacitor application ceramic capacitors have advantages and disadvan - tages. they have ultra-low esr, are non-combustible, are relatively small, and are nonpolarized. on the other hand, they?e expensive and brittle, and their ultra-low esr characteristic can result in excessively high esr zero frequencies (affecting stability). in addition, they can cause output overshoot when going abruptly from full-load to no-load conditions, unless there are some bulk tantalum or electrolytic capacitors in parallel to absorb the stored energy in the induc - tor. in some cases, there may be no room for electrolyt - ics, creating a need for a dc-dc design that uses noth - ing but ceramics. the all-ceramic-capacitor application of figure 7 has the same basic performance as the 7a standard application circuit, but replaces the tantalum output capacitors with ceramics. this design relies on having a minimum of 5m parasitic pc board trace resistance in series with the capacitor in order to reduce the esr zero frequency. this small amount of resistance is easily obtained by locating the MAX1710/max1711 circuit two or three inch - es away from the cpu, and placing all the ceramic capacitors close to the cpu. resistance values higher than 5m just improve the stability (which can be observed by examining the load-transient response characteristic as shown in the typical operating characteristics ). avoid adding excess pc board trace resistance, as there? an efficiency penalty. 5m is suffi - cient for the 7a circuit. output overshoot determines the minimum output capacitance requirement. in this example, the switching frequency has been increased to 550khz and the induc - tor value has been reduced to 0.5 h (compared to 300khz and 2 h for the standard 7a circuit) in order to minimize the energy transferred from inductor to capaci - tor during load-step recovery. even so, the amount of overshoot is high enough (80mv) that for the MAX1710, it? wise to disable ovp or use the max1711 with its fixed 2.25v overvoltage protection threshold to avoid tripping the fault latch (see the overshoot equation in the output capacitor selection section). the efficiency penalty for operating at 550khz is about 2% to 3%, depending on the input voltage. two optional 1k resistors are placed in series with fb and fbs. these resistors prevent the negative output voltage spike (that results from tripping ovp) from pulling shdn low via its internal esd diode, which tends to clear the fault latch, causing ?iccup?restarts. setting v out with a resistor-divider the output voltage can be adjusted with a resistor- divider rather than the dac if desired (figure 8). the drawback of this practice is that the on-time doesn? automatically receive correct compensation for changing output voltage levels. this can result in variable switch - ing frequency as the resistor ratio is changed and/or excessive switching frequency. the equation for adjust - ing the output voltage is: v v r r out fb = - ( ) + ? ? ? ? 1 1 1 2 % duty t t t s ns on min on min off max = + = m + = ( ) ( ) ( ) . . % 2 08 500 80 6 MAX1710/max1711 high-speed, digitally adjusted step-down contr ollers for notebook cpus ______________________________________________________________________________________ 21 dl dh fb fbs gnds v batt v out r1 1k r2 MAX1710 figure 8. setting v out with a resistor-divider
MAX1710/max1711 high-speed, digitally adjusted step-down contr ollers for notebook cpus 22 ______________________________________________________________________________________ i lim v cc v in 4.5v to 5.5v to remote load l1 0.5 m h v out 1.6v at 7a shdn 1 m f 0.1 m f 0.22 m f 470pf c2 3 x 470 m f kemet t510 irf7805 irf7805 1 m f 20 w c1 4 x 10 m f/25v d0 d1 d2 d/a inputs on/off dl lx bst dh pgnd fb 1k 1k gnd gnds fbs v dd v cc v+ MAX1710 max1711 d4** d3 ref cc ton skip ovp* 100k pgood * MAX1710 only ** max1711 only figure 9. 5v-powered, 7a cpu buck regulator where v fb is the currently selected dac value. when using external resistors, fbs remote sensing is not rec - ommended, but gnds remote sensing is still possible. connect fbs to fb and gnds to remote ground loca - tion. in resistor-adjusted circuits, the dac code should be set as close as possible to the actual output voltage so that the switching frequency doesn? become exces - sive. for highest accuracy, use the MAX1710 when adjusting v out with external resistors. the MAX1710 fb node has very high impedance, while the max1711 has a 180k 35% fb impedance, which degrades v out accuracy. adjusting v out above 2v the feed-forward circuit that makes the on-time depen - dent on battery voltage maintains a nearly constant switching frequency as v in , i load , and the dac code are changed. this works extremely well as long as fb is connected directly to the output. when the output is adjusted higher than 2v with a resis - tor-divider, the switching frequency can be increased to relatively unreasonable levels as the actual off-time decreases and isn? compensated for by a change in on- time. 3.3v is about the maximum limit to the practical adjustment range; even at the slowest ton setting and with the dac set to 2v, the switching rate will exceed 600khz. the trip threshold for output overvoltage protection scales with the nominal output voltage setting. 2-stage (5v-powered) notebook cpu buck regulator the most efficient and overall cost-effective solution for stepping down a high-voltage battery to very low output voltage is to use a single-stage buck regulator that? powered directly from the battery. however, there may be situations where the battery bus can? be routed near the cpu, or where space constraints dictate the smallest possible local dc-dc converter. in such cases, the 5v- powered circuit of figure 9 may be appropriate. the reduced input voltage allows a higher switching frequen - cy and a much smaller inductor value.
MAX1710/max1711 high-speed, digitally adjusted step-down contr ollers for notebook cpus ______________________________________________________________________________________ 23 dynamic dac code changes (max1711) changing the output voltage dynamically by switching dac codes ?n-the-fly?can be used to help make power-savings/performance trade-offs in the host sys - tem. several important design issues arise from this practice. first, know that attempting to slew the output upward quickly causes large current surges at the battery as the ic goes into output current limiting during the transition. surge currents can be controlled either by counting the dac code slowly (50khz or slower rate suggested), or by modulating the i lim current-limit threshold. the dac inputs must be driven quickly to the new value so the device doesn? wrongly interpret a disallowed dac code from the transitory value. use 100ns maxi - mum rise and fall times. selecting the output capacitors in dynamically adjusted v core applications can be tricky due to trade-offs between capacitor capacity and esr. in other words, if the capacitor has sufficiently low esr to meet the load- transient response specification, its large capacity may cause excessive input surge currents. on the other hand, a purely ceramic capacitor may not have enough capacity to prevent overvoltage during the transition from full- to no-load condition (see the overshoot equation under output capacitor selection ). it may be necessary to mix capacitor types or use specialized capacitors such as those shown in figure 7 in order to achieve the required esr while staying within the min/max capaci - tance value window. if the minimum load is very light, it may be necessary to assert forced pwm mode (via skip ) during the transition period to guarantee some output sink current capability. otherwise, the output voltage won? ramp downwards until pulled down by external load current. using forced pwm mode repeatedly to ensure sink cur - rent capability can have side effects, however. the ener - gy taken from the output by the synchronous rectifier isn? lost, but is instead returned to the input. if the fre - quency of the high-to-low output voltage transition is high enough, efficiency will be degraded by the resistive ?ric - tion?losses associated with shuttling energy between input and output capacitors. also, if the output is being overdriven by an external source (such as an external docking-station power supply), forced pwm mode may cause the battery voltage to become pumped up, possi - bly overvoltaging the battery. high-power , dynamically adjustable cpu application the max1711 v core regulator of figure 10 is designed to have its output voltage switched between 1.3v and 1.45v in less than 100 s, while causing a minimum level of input surge current. to this end, the output capacitors were selected for having the correct value to a) support the needed esr, b) prevent excess load-recovery over - shoot, and c) minimize input surge currents. the optional 74hc86 exclusive-or gate detects code transitions on each of the four most-significant dac inputs. the transition detector output goes to a precision pulse stretcher, a timer which extends the pulse for 75 s (nominal). this signal then feeds three circuits: the power-good detector, the skip input, and the ilim cur - rent-limit control input, thus reducing the current-limit threshold during the transition interval (in order to reduce battery current surges). likewise, skip going high asserts forced pwm mode in order to drag the output voltage down to the new value. forced pwm mode is incompatible with good light-load efficiency due to inductor-current recirculation losses and gate-drive loss - es. therefore, skip is driven high only during the 100 s max transition interval. the power-good output signal is the logical or of the 75 s timer signal and the max1711 pgood signal. the internal pgood detector circuit monitors only output undervoltage; pgood will probably go low during upward transitions, but not downward. the final power- good output will always go low for at least 75 s due to the timer signal. load current capability is 15a peak and 12a continuous over a 10v to 22v input range. all three mosfets require good heatsinking. see the max1711 ev kit manual for a complete bill of materials. pc board layout guidelines careful pc board layout is critical to achieving low switching losses and clean, stable operation. the switch - ing power stage requires particular attention (figure 11). if possible, mount all of the power components on the top side of the board with their ground terminals flush against one another. follow these guidelines for good pc board layout: keep the high-current paths short, especially at the ground terminals. this practice is essential for stable, jitter-free operation. tie gnd and pgnd together close to the ic. carefully follow the grounding instructions under step 4 of the layout procedure .
MAX1710/max1711 high-speed, digitally adjusted step-down contr ollers for notebook cpus 24 ______________________________________________________________________________________ irf7805 output +1.5v at 15a 10x 220 m f 4v os-con 2 x irf7805 cmpsh3 6 x 10 m f/25v ceramic 0.1 m f 1 m h/20a 1k 2 7 1 5 4 10 9 13 12 +3.3v 3m 1n4148 1n4148 1n4148 transition detector 1n4148 100k 1% 100k 1% 820pf 5% +3.3v 30k 100k 100k 2n7002 2n7002 powergood 2n7002 40k 1% 200k 1% 2n7002 timer block 2n7002 30k 49.9k 1% 0.1 m f ref cc gnd shdn d0 d1 d2 d3 d4 ton n.c. 5 9 10 2 20 19 18 17 16 8 6 21 12 11 1k 4 3 14 13 23 24 22 1 15 7 +5v input v batt 10v to 22v i lim skip pgood gnds fbs fb pgnd dl lx dh bst v cc v dd v+ 0.22 m f 0.1 m f 1 m f 2 w 20 m f ceramic 20 w 470pf 1000pf 1k 1000pf 1k 1000pf 1k 1000pf gnd b1 a1 b2 a2 b3 a3 b4 a4 3 6 8 11 14 y1 y2 y3 y4 v cc max1711 max986 74hc86 on/off lsb msb dac inputs figure 10. 15a dynamically adjustable notebook cpu supply with battery-surge current limiting
MAX1710/max1711 high-speed, digitally adjusted step-down contr ollers for notebook cpus ______________________________________________________________________________________ 25 d1 q2 v batt gnd in cout via to fb near cout+ via to lx via to source of q2 via to pgnd near q2 source inductor discharge path has low dc resistance via to fbs via to gnds gnd out v out l1 q1 cc v cc v dd ref gnd all analog grounds connect to gnd only notes: "star" ground is used. d1 is directly across q2. connect gnd to pgnd beneath ic, 1 point only. split analog gnd plane as shown. i lim MAX1710 max1711 cin figure 11. power-stage pc board layout example keep the power traces and load connections short. this practice is essential for high efficiency. the use of thick copper pc boards (2 oz. vs. 1 oz.) can en- hance full-load efficiency by 1% or more. correctly routing pc board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty. lx and pgnd connections to q2 for current limiting must be made using kelvin sense connections in order to guarantee the current-limit accuracy. with so-8 mosfets, this is best done by routing power to the mosfets from outside using the top copper layer, while tying in pgnd and lx inside (underneath) the so-8 package. when trade-offs in trace lengths must be made, it? preferable to allow the inductor charging path to be made longer than the discharge path. for example, it? better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low-side mosfet or between the inductor and the output filter capacitor. ensure that the fb connection to c out is short and direct. however, in some cases it may be desirable to deliberately introduce some trace length between the fb inductor node and the output filter capacitor (see the all-ceramic-capacitor application section). route high-speed switching nodes away from sensi - tive analog areas (cc, ref, ilim). make all pin-strap control input connections ( skip , ilim, etc.) to gnd or v cc rather than pgnd or v dd .
MAX1710/max1711 high-speed, digitally adjusted step-down contr ollers for notebook cpus 26 ______________________________________________________________________________________ 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 dh lx bst skip fbs fb shdn v+ top view d0 d1 d2 d3 ton v cc ilim cc 16 15 14 13 9 10 11 12 ovp v dd pgnd dl pgood gnds gnd ref qsop MAX1710 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 dh lx bst skip fbs fb shdn v+ top view d0 d1 d2 d3 ton v cc ilim cc 16 15 14 13 9 10 11 12 d4 v dd pgnd dl pgood gnds gnd ref qsop max1711 pin configurations layout procedure 1) place the power components first, with ground termi - nals adjacent (q2 source, cin-, cout-, d1 anode). if possible, make all these connections on the top layer with wide, copper-filled areas. 2) mount the controller ic adjacent to mosfet q2, preferably on the back side opposite q2 in order to keep lx-pgnd current-sense lines and the dl gate- drive line short and wide. the dl gate trace must be short and wide, measuring 10 to 20 squares (50 to 100 mils wide if the mosfet is 1 inch from the con - troller ic). 3) group the gate-drive components (bst diode and capacitor, v dd bypass capacitor) together near the controller ic. 4) make the dc-dc controller ground connections as shown in figure 11. this diagram can be viewed as having three separate ground planes: output ground, where all the high-power components go; the pgnd plane, where the pgnd pin and v dd bypass capaci - tor go; and an analog gnd plane, where sensitive analog components go. the analog ground plane and pgnd plane must meet only at a single point directly beneath the ic. these two planes are then connected to the high-power output ground with a short connection from v dd cap/pgnd to the source of the low-side mosfet, q2 (the middle of the star ground). this point must also be very close to the out - put capacitor ground terminal. 5) connect the output power planes (v core and system ground planes) directly to the output filter capacitor positive and negative terminals with multiple vias. place the entire dc-dc converter circuit as close to the cpu as is practical.
MAX1710/max1711 high-speed, digitally adjusted step-down contr ollers for notebook cpus ______________________________________________________________________________________ 27 package infor mation qsop.eps
MAX1710/max1711 high-speed, digitally adjusted step-down contr ollers for notebook cpus 28 ______________________________________________________________________________________ notes

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